The overall performance of a computer processor is often limited by the ability of the processor to rapidly and efficiently respond to events. This is particularly true when the events are frequent and diverse in nature and when the handling of some or all of the events is a function of the state of the software machine that responds to the events. Therefore, the need exists for a computer processor that can respond with comparable efficiency to both:                (i) events whose handling is independent on the state of the software machine that responds to the events, and        (ii) events whose handling is dependent on the state of the software machine that responds to the events.        